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| Preliminary Technical Data FEATURES True rms response detector Envelope output with peak hold option Excellent temperature stability 0.25 dB rms detection accuracy vs. temperature 0.25 dB envelope detection accuracy vs. temperature; over the top 15 dB of the input range Over 30 dB input power dynamic range, inclusive of crest factor, up to 3.8 GHz RF bandwidths from 800 MHz to 3.8 GHz Envelope bandwidths of 10 MHz 500 input impedance Single-supply operation: 2.7 V to 3.5 V Low power: 5 mA at 3 V supply RoHS compliant 800 MHz to 3800 MHz Crest Factor Detector ADL5502 Figure 1. APPLICATIONS Power and envelope measurement of W-CDMA, CDMA2000, and QPSK-/QAM-based OFDM, and other complex modulation waveforms RF transmitter or receiver power and envelope measurement GENERAL DESCRIPTION The ADL5502 is a mean-responding power detector in combination with an envelope detector to accurately determine the crest factor of a modulated signal. It can be used in high frequency receiver and transmitter signal chains from 800 MHz to 3.8 GHz with envelope bandwidths over 10 MHz. Requiring only a single supply between 2.7 V and 3.5 V, the detector draws less than 5 mA. The input is internally ac-coupled and has a nominal input impedance of 500 . The rms output is a linear-responding dc voltage with a conversion gain of 2.0 V/Vrms at 900 MHz. The envelope output with a conversion gain of 1.4 V/V can be toggled between real-time envelope measurement or peak hold with less than TBD mV droop in over 200 S. The ADL5502 is a highly accurate, easy to use means of determining the peak to average value of complex waveforms. It can be used for crest factor measurements of both simple and complex waveforms, but is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as CDMA2000, W-CDMA, and QPSK/QAM-based OFDM waveforms. The peak hold function allows the capture of short peaks in the envelope with lower sampling rate ADC's. The crest factor detector operates from -40C to +85C and is available in an 8-ball, 1.5 mm x 1.5 mm wafer-level chip scale package. It is fabricated on a high fT silicon BiCMOS process. Rev. PrD (04/20/2008) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADL5502 SPECIFICATIONS Preliminary Technical Data TA = 25C, VS = 3.0 V, RFLT = 100 nF, light condition 600 LUX, unless otherwise noted. Including 50 ohm input termination resistor. Table 1. Parameter FREQUENCY RANGE RMS CONVERSION (f = 450 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In ENVELOPE CONVERSION Dynamic Range1 0.25 dB Error2 1 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In RMS TO ENVELOPE TRACKING 0.25 dB Error 1 dB Error 2 dB Error RMS CONVERSION (f = 800 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Condition Input RFIN Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Input RFIN to output VENV CF=3.5 dB, -40C < TA < +85C VS = 3 V VS = 3 V 0.25 dB error3 1 dB error3 Min 450 Typ Max 3800 Unit MHz ||pF dB dB dB dBm dBm V/V rms V V V TBD||TBD 15 25 30 TBD TBD 1.82 0.001 TBD TBD PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms 15 30 TBD TBD 1.4 TBD TBD TBD 15 25 30 331||1.0 15 25 30 TBD TBD 1.81 0.001 TBD TBD dB dB dBm dBm V/V V V V dB dB dB ||pF dB dB dB dBm dBm V/V rms V V V Rev. PrD (04/20/2008) | Page 2 of 14 Preliminary Technical Data Parameter RMS CONVERSION (f = 900 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In RMS CONVERSION (f = 1900 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In RMS CONVERSION (f = 2350 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In RMS CONVERSION (f = 2700 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In Condition Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Min Typ 316||0.9 15 25 30 TBD TBD 1.80 0.001 TBD TBD 215||0.9 15 25 30 TBD TBD 1.75 -0.005 TBD TBD TBD||TBD 15 25 30 TBD TBD 1.56 -0.004 TBD TBD TBD||TBD 15 25 30 TBD TBD 1.53 -0.006 TBD TBD Max ADL5502 Unit ||pF dB dB dB dBm dBm V/V rms V V V ||pF dB dB dB dBm dBm V/V rms V V V ||pF dB dB dB dBm dBm V/V rms V V V ||pF dB dB dB dBm dBm V/V rms V V V Rev. PrD (04/20/2008) | Page 3 of 14 ADL5502 Parameter RMS CONVERSION (f = 3500 MHz) Input Impedance Dynamic Range1 0.25 dB Error2 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage--High Power In Output Voltage--Low Power In VRMS OUTPUT Output Offset Response time Available Output Current VENV OUTPUT Envelope Modulation Bandwidth Maximum Output Voltage Output Offset Response time Available Output Current PEAK HOLD Hold Time Hold Voltage Drop CONTROL INTERFACE Logic Level to, Real Time Envelope, HI Input Current when HI Logic Level for Peak Hold Condition, LO Enable Time Disable Time ENABLE INTERFACE Logic Level to Enable Power, HI Condition Input Current when HI Logic Level to Disable Power, LO Condition Power-Up Response Time5 POWER SUPPLIES Operating Range Quiescent Current Disable Current 1 2 Preliminary Technical Data Condition Input RFIN to output VRMS CW input, -40C < TA < +85C VS = 3 V VS = 3 V VS = 3 V 0.25 dB error 1 dB error VRMS = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms Pin VRMS No signal at RFIN 5 dB Step, 10% to 90% of settling level, no filter cap Pin VENV 5 Vs = 2.7 V, RLOAD 10 k No signal at RFIN 5 dB Step, 10% to 90% of settling level, no filter cap 10 1.5 TBD TBD 3 100 200 TBD VPOS 0.1 +0.5 MHz V mV S mA S mV/ S V A V s s V A V s s V mA A Min Typ TBD||TBD 15 25 30 TBD TBD 1.33 -0.005 TBD TBD 150 15 3 Max Unit ||pF dB dB dB dBm dBm V/V rms V V V mV S mA 2.7 V VS 3.5 V, -40C < TA < +85C 2.7 V at ENBL, -40C TA +85C 2.7 V VS 3.5 V, -40C < TA < +85C CFLTR = Open, 0 dBm at RFIN CFLTR = 100 nF, 0 dBm at RFIN Pin ENBL 2.5 V VS 3.5 V, -40C < TA < +85C 2.5 V at ENBL, -40C TA +85C 2.5 V VS 3.5 V, -40C < TA < +85C CFLTR = Open, 0 dBm at RFIN CFLTR = 100 nF, 0 dBm at RFIN -40C < TA < +85C No signal at RFIN6 ENBL in LO Condition, no signal at RFIN 1.8 0.05 -0.5 TBD TBD 1.8 0.05 -0.5 TBD TBD 2.5 5.0 < TBD VPOS 0.1 +0.5 3.5 5 The available output swing, and hence the dynamic range, is altered by the supply voltage; see TBD. Error referred to delta from 25C response. 3 Error referred to best-fit line at 25C 4 Calculated using linear regression. 5 The response time is measured from 10% to 90% of settling level 6 Supply current is input level dependant; see TBD. Rev. PrD (04/20/2008) | Page 4 of 14 PRELIMINARY TECHNICAL DATA ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VS VRMS, VPK/ENV, ENBL, PK/ENV RFIN Equivalent Power, re 50 Internal Power Dissipation JA (SC-70) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 3.5 V 0 V, VS 1.25 V rms 15 dBm TBD mW TBDC/W 125C -40C to +85C -65C to +150C ADL5502 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD (04/20/2008) | Page 5 of 14 ADL5502 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Preliminary Technical Data Figure 2. 8-Bump WLCSP Configuration Table 3. Pin Function Descriptions Ball No. 1 2 3 4 5 6 7 8 Mnemonic FLTR VPOS RFIN COMM PK/ENV VPK/ENV VRMS ENBL Description Modulation Filter Pin. Connection for an External Capacitor to lower the corner frequency of the modulation filter Supply Voltage Pin. Operational range 2.7 V to 3.5 V. Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 500 input impedance. Device Ground Pin. Control Pin. Connect pin to ground for real-time envelope measurement mode. Connect pin to VS for peak-hold mode. Reset peak-hold by placing device in real-time envelope measurement mode. Envelop Output. Function can switched between real-time envelop measurement or peak-hold using PK/ENV. RMS Output Pin. Rail-to-rail voltage output with limited current drive capability. The output has an internal TBD k series resistance. High resistive loads are recommended to preserve output swing. Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode. Rev. PrD (04/20/2008) | Page 6 of 14 PRELIMINARY TECHNICAL DATA TYPICAL PERFORMANCE CHARACTERISTICS ADL5502 TA = 25C, VS = 3.0 V, CFLTR = open, COUT = 4.7 nF, Colors: black = +25C, blue = -40C, red = +85C, unless otherwise noted. 2.0 450 MHz 1.5 1.0 ERROR (dB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -25 -20 -15 -10 -5 INPUT (dBm) 0 5 10 15 900 MHz 1900 MHz 2350 MHz 2700 MHz 3500 MHz Figure 3. VRMS Output vs. Input Level, Frequencies 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 3500 MHz, Supply 3.0 V Figure 6. VRMS Linearity Error vs. Input Level, Freq 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 3500 MHz, Supply 3.0 V Figure 4. VRMS Output vs. Input Level (Linear Scale), Freq 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 3500 MHz, Supply 3.0 V Figure 7. Input Impedance vs. Frequency, Supply 3.0 V, Temperatures -40C, +25C, and +85C 3 2 1 Error - dB 0 -1 -2 -3 -25 -20 -15 -10 -5 Pin - dBm 0 5 10 15 Figure 5. VRMS Temperature Drift Distributions for Multiple Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 900 MHz Figure 8. VRMS Delta from +25C Output Voltage for Multiple Devices at -40C and +85C, Frequency 900 MHz Rev. PrD (04/20/2008) | Page 7 of 14 ADL5502 Preliminary Technical Data Figure 9. VRMS Temperature Drift Distributions for Mulitple Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency1 900 MHz Figure 12. VRMS Delta from +25C Output Voltage for Multiple Devices at -40C and +85C, Frequency 1900 MHz Figure 10. VRMS Temperature Drift Distributions for Mulitple Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 2350 MHz 1.0 CW Figure 13. VRMS Delta from +25C Output Voltage for Multiple Devices at -40C and +85C, Frequency 2350 MHz 1.00 CW 0.8 0.6 0.4 ERROR (dB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -20 12.2kbps, DPCCH (-5.46dB, 15kSPS) +DPDCH (0dB, 60kSPS), 3.4dB CF 768kbps, DPCCH (-11.48dB, 15kSPS) +DPDCH1 + 2 (0dB, 960kSPS), 5.8dB CF PICH + FCH (9.6kbps) + SCH (153.6kbps), 6.7dB CF PICH + FCH (9.6kbps) + DCCH, 6.3dB CF PICH + FCH (9.6kbps) + DCCH +SCH (153.6kbps), 7.6dB CF 0.80 DPCCH (15ksps, SC0, -5.46 dB) + DPDCH (60ksps, SC16, 0 dB), 3.55 dB CF 0.60 0.40 ERROR (dB) 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 DPCCH (15ksps, SC0, -6.02 dB) + DPDCH (60ksps, SC16, -4.08 dB) + HS-DPCCH (15ksps, SC64, 0 dB), 4.91 dB CF DPCCH (15ksps, SC0, -6.02 dB) + DPDCH (60ksps, SC16, -11.48 dB) + HS-DPCCH (15ksps, SC64, 0 dB), 5.34 dB CF DPCCH (15ksps, SC0, -6.02 dB) + HS-DPCCH (15ksps, SC64, 0 dB), 5.44 dB CF -15 -10 -5 0 INPUT (dBm) 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 11. VRMS Error from CW Linear Reference vs. Input with Various WCDMA & CDMA2000 Rev Link Waveforms at 1900 MHz, CFLTR = 22 nF Figure 14. VRMS Error from CW Linear Reference vs. Input with Various WCDMA HSPA Reverse Link Waveforms at 1900 MHz, CFLTR = 22 nF Rev. PrD (04/20/2008) | Page 8 of 14 PRELIMINARY TECHNICAL DATA ADL5502 v Figure 15.v Envelope Error (representative of Crest Factor) from rms Reference vs. Input with Various WCDMA and CDMS2000 Reverse Link Waveform,; at 1900 MHz, CFLTR = 22 nF, COU = 4.7 nF, Figure 16. Peak Hold Response Time Rev. PrD (04/20/2008) | Page 9 of 14 ADL5502 APPLICATIONS BASIC CONNECTIONS Figure 17 shows the basic connections for the ADL5502. The device is powered by a single supply between 2.5 V and 3.5 V, with a quiescent current of 5 mA. The VPOS pin is decoupled using 100 pF and 0.1 F capacitors. Placing a single 75 resistor at the RF input provides a broadband match of 50 Ohms. More precise resistive or reactive matches can be applied for narrow frequency band use (see impedance plot, Figure 7). The rms averaging can be augmented by placing additional capacitance at CFLT. The ac residual can be further reduced by increasing the output capacitance, COUT. The combination of the internal 100 output resistance and COUT produce a lowpass filter to reduce output ripple of the VRMS output. Note that a minimum of 4.7 nF capacitive load should be kept on the RMS output. To operate the device in peak-hold mode, the control line must be temporally set to HI (reset or envelope mode) and then set back to LO (peak-hold mode). This allows the ADL5502 to be initialize to a known state. Preliminary Technical Data Figure 17. Basic Connections for ADL5502 EVALUATION BOARD Figure 18 shows the schematic of the ADL5502 evaluation board. The board is powered by a single supply in the 2.5 V to 3.5 V range. The power supply is decoupled by 100 pF and 0.1 F capacitors. Table 4 details the various configuration options of the evaluation board. Figure 19 and Figure 20 show the component and circuit layouts of the evaluation board. The RF input has a broadband match of 50 Ohms using a single 75 resistor at R10. More precise matching at spot frequencies is possible using the pads for components C15, C16, and R10. The two outputs, accessible via the SMAs labeled VRMS and VENV, provide the rms response and the envelope/peak-hold vmeasurement of the RF input power level. The device must be enabled by switching SW1 to HI (setting the switch to the position opposite that of the "SW1" label). The device is place in peak-hold mode by placing switch SW2 in the position closes to the "SW2" label. Envelope-tracking mode is possible by setting SW2 in the opposite switch position (away from the "SW2" label). A signal generator can drive the control mode via the SMA labeled CNTL (see Table 4 for more details). OPERATING IN PEAK-HOLD MODE To operate the device in peak-hold mode, the control line must be temporally set to HI (envelope mode) and then set back to LO (peak-hold mode). This allows the ADL5502 to be initialize to a known state. For envelope mode or rms use only, the control line can simply be set to HI. Rev. PrD (04/20/2008) | Page 10 of 14 PRELIMINARY TECHNICAL DATA ADL5502 Figure 18. Evaluation Board Schematic Figure 19. Layout of Evaluation Board, Component Side Figure 20. Layout of Evaluation Board, Circuit Side Rev. PrD (04/20/2008) | Page 11 of 14 ADL5502 Table 4. Evaluation Board Configuration Options Component VPOS, GND C13, C14 C17 R10, C15, C16 Description Ground and Supply Vector Pins. Power Supply Decoupling. Nominal supply decoupling of 0.01 F and 100 pF. Preliminary Technical Data R3, R6, R11, R12, C18, C19 Filter Capacitor. The internal rms averaging capacitor can be augmented by placing additional capacitance in C17. RF Input interface. The 75 resistor at R10 combines with the ADL5502 internal input impedance to give a broadband input impedance of around 50 . The pads for components C15, C16, and R10 can be used for more precise matching at a particular frequency. Output Filtering. The combination of the internal 100 output resistance and C18 produce a low-pass filter to reduce output ripple of the VRMS output. Similarly, C19 and the internal 100 output resistance will form a low-pass filter to at the VPK/ENV output. Either output can be scaled down using the resistor divider pads, R3, R11, R6, and R12. Note that a minimum of 4.7 nF capacitive load should be kept on the RMS output. Device Enable. When the switch is set towards the "SW1" label, the ENBL pin is grounded (through the 0 resistor) putting the device in power-down mode. In the opposite switch position, the ENBL pin is connected to VPOS and the ADL5502 is in operating mode. While the switch is in the disabled position, the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R1 must be removed or changed to provide a 50 match. Control Interface. When the switch is set towards the "SW2" label, the PK/ENV pin is grounded (through a 10 k resistor) putting the device in peak-hold mode. In the opposite switch position, the pin is connected to VPOS (through a 10 k resistor) and the ADL5502 is in envelope-tracking mode. While the switch is in the peak-hold position, the PK/ENV pin can be driven by a signal generator via the SMA labeled CNTL. In this case, R8 may be removed or changed to provide a 50 match. R13 and C20 allow for low-pass filter design for the control pin. Alternate Interface. The end connector, P1, allows access to various ADL5502 signals. These signal paths are only used during factory test and characterization. Default Condition Not Applicable C13 = 0.1 F (Size 0402) C14 = 100 pF (Size 0402) C17 = Open (Size 0402) R10 = 75 (Size 0402) C15, C16 = 0 (Size 0402) R11, R12 = Open (Size 0402) R3, R6 = 0 (Size 0402) C18 = 4.7 nF (Size 0402) C19 = Open (Size 0402) R1 = 0 (Size 0402) SW1 = away from "SW1" label R1, SW1 R7, R8, R13, C20, SW2 R7, R8 = 10 k (Size 0402) R13 = 0 (Size 0402) C20 = Open (Size 0402) SW2 = away from "SW1" label R2, R4, R5, R9 = 0 (Size 0402) C11 = 0.1 F (Size 0402) C12 = 100 pF (Size 0402) R2, R4, R5, R9, C11, C12 Rev. PrD (04/20/2008) | Page 12 of 14 PRELIMINARY TECHNICAL DATA OUTLINE DIMENSIONS ADL5502 Figure 21. 8-Bump Wafer Level Chip Scale Package [WLCSP] (TBD) Dimensions shown in millimeters ORDERING GUIDE Model ADL5502ACBZ-P71 ADL5502ACBZ-P21 ADL5502-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C Package Description 8-Lead WLCSP, 7" Pocket Tape and Reel 8-Lead WLCSP, 7" Pocket Tape and Reel Evaluation Board Package Outline KS-8 KS-8 Branding TBD TBD Ordering Quantity 3,000 250 Z = Pb-free part. Rev. PrD (04/20/2008) | Page 13 of 14 ADL5502 NOTES Preliminary Technical Data (c) 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07631-0-6/08(PrD) Rev. PrD (04/20/2008) | Page 14 of 14 |
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